1. Field of the Invention
This invention is related to the field of processors and, more particularly, to magnitude comparators in processors.
2. Description of the Related Art
Processors often are designed to perform a magnitude comparison of a pair of operands. As used herein, a magnitude comparison is a comparison which determines the relative magnitude of the operands (e.g. one operand being greater than or less than the other operand). The result of the comparison is a value which indicates the relative magnitude. For example, the result may indicate whether or not a first operand is greater than a second operand. Alternatively, the result may indicate whether or not the first operand is less than the second operand, greater than or equal to the first operand, less than or equal to the second operand, any combination of the above, etc.
Magnitude comparisons may be during execution of a variety of instructions. For example, a magnitude comparison may be used in some instruction sets when executing a conditional branch instruction, comparing two operands of the branch instruction and conditionally taking or not taking the branch in response to the result of the magnitude comparison. Some instruction sets include instructions which conditionally cause an exception (e.g. the trap instructions in the MIPS instruction set) based on a magnitude comparison of two operands of the instruction. Other instructions may be defined to write a register with a binary one or zero based on the result of the comparison of two operands of such instructions. For example, the MIPS instruction set includes set instructions which are defined to write a general purpose register with the result of a magnitude comparison. Another example of such instructions may be compare instructions included in many instruction sets. Compare instructions may write any register with a result (or multiple bits of results, such as greater than, less than, equal, etc.). Often, compare instructions update a special condition code (or flags) register with multiple bits of result based on a magnitude comparison.
Typically, magnitude comparisons are performed in processors using a full adder to subtract a first of the two operands to be compared from the second of the two operands. The sign of the result of the subtraction indicates whether or not the first operand is greater than the second operand.